The present invention relates generally to analog circuits, and in particular low dropout linear regulators and systems which incorporate low dropout linear regulators.
Most linear regulators have feedback which needs some type of stability compensation, either external or internal compensation. To obtain more precise voltage regulation, larger gain is required which inherently makes the feedback less stable. These two trade-offs, large gain and stability, create a design challenge. Other design considerations require low current, reduced silicon area, and good power supply rejection. Many techniques have been implemented for stability compensation. The following patents constitute a sampling of conventional solutions: U.S. Pat. Nos. 4,908,566, 5,168,209, 5,637,992, 5,648,718, 5,744,944, 5,850,139, 5,945,818, 5,982,226, and 6,522,112. All of these techniques use some type of internal zero compensation.
FIG. 3 shows a simplified open loop transfer function of a linear regulator. A regulator with feedback becomes unstable if the open loop gain is >0 dB and the phase is −180 degrees. This condition occurs if at least 2 poles exist below the unity gain bandwidth (UGB). The zero compensation method from the cited patents essentially adds 90 degrees back to the transfer function and keeps the loop stable. Methods to add zero compensation typically increase the power requirement of the circuit and increase the silicon area, especially if large capacitors are needed in silicon.
The P0 pole in FIG. 3 is typically caused by a main compensating load capacitor C1, as shown in FIG. 4. Pa of FIG. 3 represents a secondary pole that can be caused by parasitic capacitive loading (Cp1) at the gate of T1 or by a parasitic capacitance (Cp2) at the base of Tpass, or even by the OpAmp itself. In general, a circuit arrangement can cause stability problems if at least 2 poles exist below the UGB (i.e., less than the unity gain frequency) and no zero compensation is provided.
In essence there are many places where secondary poles can exist. As in FIG. 4, nodes V1, V3, Vf, Vout and the OpAmp are potential areas where poles exist. Node V3, however, can be the most difficult node to keep sufficiently low in parasitic capacitance, since it has to drive off the chip and at the base of the Pass transistor resulting in 10's of pF's.
The other traditional method of stability compensation is to rely on the ESR (equivalent series resistance) of the load capacitor. The ESR of the load capacitor can provide a compensating zero to offset the extra pole in the feedback typically from the amplifier stage. The issue with relying on the ESR of the capacitor is there can be a narrow range of ESR values allowed for a given design.
There is need for an integrated linear regulator have relatively large gain while maintaining stability, with reduced chip layout area and reduced power consumption.